Sense amplifier circuits are employed in memory devices to read a content of memory cells and to provide an output signal indicative of a logical value stored in the cells. Both volatile (e.g., SRAM) and non-volatile (e.g., FLASH) memories employ sense amplifiers. One form of memory, termed FLASH memory, is particularly attractive for applications requiring non-volatile storage with large memory capacity and relatively low cost. The advancement of semiconductor technology has resulted in a continual improvement in the performance of all memory systems, and FLASH memory systems in particular, as measured by attributes such as power, storage capacity, speed, and cost. These performance attributes are favorably impacted by ongoing reductions in device feature size and operating voltage. As memory cell sizes decrease, the available sense current and voltage are reduced. Therefore, sense amplifier performance must improve.
What is needed, therefore, is a method for realizing a high performance sense amplifier which takes advantage of CMOS fabrication processes in order to provide low power consumption, high speed operation, high sensitivity, and low silicon area consumption.